Events - Seminars

Implementing MATLAB & Simulink algorithms in FPGAs

Seminar Overview

The MathWorks and Xilinx would like to invite you to attend this free seminar to learn about efficient implementation methods of MATLAB® & Simulink algorithms in Xilinx FPGAs. MathWorks HDL code generation solutions are a fast developing area with a lot of new features with every release. Come and see how R2010a can improve your workflow today.

HDL code generation and verification tools from The MathWorks extend the Model-Based Design methodology. MathWorks provides you with a single integrated tool environment for the implementation of algorithms in FPGAs. Abstract simulation models are incrementally refined until automatic HDL code generation enables the implementation in an FPGA. This results in an acceleration of the complete development process.

The following topics will be covered:

Optimal choice of modelling methods (MATLAB/Simulink/Stateflow)
Analyzing several system architectures and making architectural trade-offs
Transitioning from floating to fixed-point data types
HDL code generation
Verification through co-simulation
What’s new in R2010a for HDL code generation?

Using real examples, you will gain insight into using the Model-Based Design methodology for developing algorithms for hardware implementation.

This seminar includes a guest presentation by Olivier Tremois, DSP Specialist from Xilinx, on the Xilinx silicon product portfolio, how to accelerate rapid prototyping through Hardware-In-the-Loop simulations, and how to further leverage FPGA specific resources using System Generator.

Note: we are very sorry but this seminar is full. If you wish to be placed on the waiting list, please send an E-mail to contact@mathworks.nl

Thank you for your interest in MathWorks Seminars. There are no dates currently scheduled for this Seminar. For more information on our seminars and products contact MathWorks sales or please visit:

Who Should Attend

Prior knowledge of The MathWorks products is not required. This free-of-cost seminar is recommended to anyone who is working in the development of applications for FPGAs/ASICs, especially:

System architects and system engineers
Algorithm designers
Hardware developers
FPGA/ASIC designers
Project managers
Team leaders

Seminar Highlights

What’s new in R2010a for HDL code generation?
VHDL & Verilog code generation from Embedded MATLAB, Simulink & Stateflow
Filter Design and HDL code generation
Fixed-Point design in MATLAB & Simulink
Generating test benches
Co-simulation with HDL simulators
Verification
Xilinx implementation tools
Xilinx devices
Hardware In the Loop

Agenda
13.00	Registration
13.30	Welcome & Introduction
13.45	Reduce your hardware development time with Model-Based Design Model-Based Design Methodology Simulink introduction Design & Implementation of a Sobel Edge Detection Algorithm
14:40	Coffee break
14:55	Automatic HDL Code Generation and Integrated HDL Verification Using Simulink HDL Coder in a Design-Flow Environment HDL Code generation Optimizing a Design Working with Synthesis Tools Continuous Verification with MATLAB & Simulink Functional Verification using Co-simulation Verification strategies
15:50	Coffee break
16.05	Guest presentation: Xilinx FPGA Hardware Implementation Flow By Olivier Tremois, DSP Specialist from Xilinx Virtex-6 / Spartan-6 family overview Implementing the algorithm in physical hardware Speeding up rapid prototyping through Hardware In the Loop Leveraging dedicated FPGA resources using System Generator
17:00	Summary and Q&A
17:15	Closing

Products & Services	Solutions	Academia	Support	User Community	Company